Due to the continual reductions in minimum feature size of electronic components such as transistors and capacitors and the continual increasing of application complexities, semiconductor Integrated Circuits (ICs) are increasingly more complex with millions of electronic components connected together to perform intended functions. These smaller electronic components also require smaller packages that utilize less area than packages of the past. One type of smaller package that has been developed is three-dimensional (3D) ICs, in which two die or multiple die or ICs are bonded together and electrically connected between the die and contacts on an interposer.
Modern IC design, fabrication, and packaging rely heavily on the use of various software tools, called computer aided design (CAD) tools or electronic design automation (EDA) tools, which perform the tasks required to implement desired circuit functions onto silicon. An IC design may start with a software description, e.g., in a programming language such as C or VHDL, of the functionality of the circuit, which is then synthesized to generate a logic “netlist” containing a description of the interconnected gate-level hardware elements.
The physical design process follows the synthesis step, where the hardware elements and their connections are physically laid out, represented as placements of geometric shapes, often referred to as a layout, on a variety of layers to be fabricated on the semiconductor device. Physical design operations may comprise: design netlist (after synthesis), floorplanning, placement, routing, physical verification, generation of layout data, which will be used for fabrication. After the die have been fabricated, multiple die may be packaged together using 3D IC technology or other packaging technologies. Throughout this description, the word die may be used to refer to a singular die or plural dies.
The traditional serialized design flow of digital systems, e.g., logic synthesis followed by floorplanning, placement, and routing, introduces potential optimization disconnects. Optimization decisions made at one stage may not correlate well with the solution quality at a next stage. The current CAD tools are further limited to the design flow within a die, instead of dealing with multiple die in a package. Therefore there is a need to combine the floorplanning with placement and routing, and to deal with multiple die in a package level as well.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.